Engineering Guides · Module 04
CAN and CAN-FD: topology, termination, bit timing
A CAN bus is a terminated twisted pair; every node must use the same bit timing, with the sample point near the end of the bit.
Assumptions: Numbers in the examples are illustrative and the code is executed by the site’s tests. Facts taken from a cited source are marked; other statements are general engineering knowledge and must be confirmed on the datasheet of the part you use.
1. Engineering problem
CAN connects motor drivers, batteries and sensors over a shared pair of wires with built-in error detection. It works only if the bus is terminated and every node samples bits at compatible times.
2. When is this needed?
- Connecting motor controllers, a BMS or distributed actuators.
- When a CAN bus shows error frames or bus-off events.
- When configuring a microcontroller CAN peripheral.
3. Selection and design decisions
Sourced facts (Wikipedia, citing ISO 11898): high-speed CAN (ISO 11898-2) uses a twisted pair with a nominal 120 Ω characteristic impedance on a linear bus, terminated at each end with a 120 Ω resistor; the bit speed is up to 1 Mbit/s on classic CAN and 5 Mbit/s on CAN FD; a classic frame carries up to 8 bytes and a CAN FD frame up to 64 bytes; in CAN FD, data length codes 9 to 15 mean 12, 16, 20, 24, 32, 48 and 64 bytes.
| Item | Rule |
|---|---|
| Topology | Linear bus with short stubs; no long branches or stars for high-speed CAN |
| Termination | 120 Ω at each end of the bus (about 60 Ω measured between CANH and CANL with power off) |
| Bit timing | All nodes use the same bit rate and compatible sample point; bit time = 1 + segment 1 + segment 2 time quanta |
| Bus load | Keep below about 50 % for margin on a control bus (a design practice, not a standard) |
| CAN FD | A faster data phase needs shorter stubs and tighter sample-point settings; all nodes must support FD |
4. Advantages and disadvantages
- Classic CAN is simple and universal; CAN FD carries more data per frame at higher speed and needs FD-capable nodes everywhere.
- Higher bit rate shortens the maximum bus length.
- More nodes increase capacitance and bus load.
5. Requirements and constraints
- Exactly two termination resistors, at the physical ends.
- Cable is twisted pair with the right impedance.
- Bit rate, sample point and (for FD) data-phase rate agree across nodes.
6. Architecture
node A ──stub──┬────────────── twisted pair (CANH/CANL) ──────────────┬──stub── node D
120 Ω ───────┘ node B node C └─────── 120 Ω7. Implementation
- Choose the bit rate from the bus load and length.
- Lay out a linear bus; terminate both ends and nothing else.
- Choose prescaler and segment lengths so the bit rate is exact (below).
- Set the sample point (commonly 75 % to 87.5 %: check the device and transceiver guidance).
- Measure the resistance between CANH and CANL with power off and view the waveform.
def bit_timing(clk, prescaler, seg1, seg2):
tq = 1 + seg1 + seg2
return clk / (prescaler * tq), (1 + seg1) / tq * 100
for p, s1, s2 in ((5, 13, 2), (4, 16, 3), (8, 7, 2)):
rate, sp = bit_timing(40e6, p, s1, s2)
print(f"prescaler {p}, seg1 {s1}, seg2 {s2}: {rate / 1000:.1f} kbit/s, sample point {sp:.1f} %")
DLC = {9: 12, 10: 16, 11: 20, 12: 24, 13: 32, 14: 48, 15: 64}
print("CAN FD DLC 0-8 =", "0-8 bytes; DLC 9..15 ->", [DLC[k] for k in sorted(DLC)])Printed (checked by the site’s tests):
prescaler 5, seg1 13, seg2 2: 500.0 kbit/s, sample point 87.5 %
prescaler 4, seg1 16, seg2 3: 500.0 kbit/s, sample point 85.0 %
prescaler 8, seg1 7, seg2 2: 500.0 kbit/s, sample point 80.0 %
CAN FD DLC 0-8 = 0-8 bytes; DLC 9..15 -> [12, 16, 20, 24, 32, 48, 64]Reading it: with a 40 MHz CAN clock all three settings give exactly 500 kbit/s (clock ÷ (prescaler × time quanta per bit)) but with sample points of 87.5 %, 85 % and 80 %. Choose per the transceiver and bus length. The DLC mapping line shows that CAN FD data lengths above 8 bytes are not linear (9 → 12, 15 → 64). The clock rate is illustrative.
8. Real examples
- AMR: wheel motor drivers and BMS on a 500 kbit/s CAN bus, terminated at the controller and at the last driver.
9. Failure scenarios
- Termination at every node (low resistance) or none at all, causing errors.
- A star topology with long stubs.
- Two nodes with different sample points that never agree.
10. Troubleshooting
- Error frames: check termination, ground and bit rates.
- Bus-off: look for a node with wrong timing or a shorted line.
- Intermittent errors at speed: shorten stubs, add shielding or lower the rate.
11. Validation
- The example prints the lines shown (executed by the site tests).
- Resistance between CANH and CANL is about 60 Ω with power off.
- Error counters stay at zero over a long run with the motors active.
12. Engineering checklist
13. Further references
- Wikipedia, CAN bus and CAN FD, read 2026-11-06 (secondary source; the standards are ISO 11898, which was not read).
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