UAV Systems Engineering · M7-L1 · Hands-on lab (runs on your machine)

Measure ROS 2 end-to-end latency

Build a latency probe, run it under load, and report p50, p99 and the stage that causes the tail.

Embedded Systems, Timing and System Integration
Implementation-specific
About 75 minutes

What you will do

You will add timestamps at the source of a ROS 2 pipeline, measure now − stamp at each stage and at the output, and analyse the results with the tools of lesson M7-T6. The pipeline can be any chain of two or three nodes on your machine (for example a camera or rosbag player, a feature-tracking node, and a pose publisher); use the lesson’s analysis script for the statistics.

Before you start

ROS 2 installed and a bag or a synthetic publisher at a known rate.
Lessons M7-T5 and M7-T6.

Steps

Make the source publish messages whose header.stamp is the acquisition time (for a bag, the recorded stamp; for a synthetic source, the time just before publishing).
In each stage, forward the original stamp unchanged and log now − stamp on output (a few lines in the node).
Use ros2 topic delay <topic> as a quick cross-check where the messages have headers.
Run for at least 5 minutes at the target rate; save per-message latencies; compute p50, p95, p99, max and the deadline-miss rate (lesson M7-T6 script).
Repeat with a CPU load (stress-ng or a heavy node) and with different QoS settings (depth, reliability).

# inside a ROS 2 node callback (message has a header):
now = self.get_clock().now().nanoseconds
stamp = msg.header.stamp.sec * 1_000_000_000 + msg.header.stamp.nanosec
self.latencies.append((now - stamp) / 1e6)       # milliseconds
# on shutdown: np.save('latency_stageN.npy', np.array(self.latencies))

Latency probe fragment.

How to know it worked

A table of p50, p95, p99, max and miss rate for each stage and end-to-end.
A statement of which stage dominates the tail, with a plot of its distribution.
A comparison with and without load.

If it does not work

Troubleshooting
Symptom	Likely cause	What to check
Negative latencies	Clock mismatch or sim time vs wall time	Use one clock source; set `use_sim_time` consistently
Latency grows steadily	Stage slower than input rate; unbounded queue	Reduce the rate or the work; use depth-1 queues
Stage latencies do not add up	A hidden queue or driver buffer	Add a timestamp at the middleware boundary

References

Record your progress

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